A technique for configuring one semiconductor memory device by stacking a plurality of memory core chips and one interface chip has been proposed. The interface chip is connected to the plurality of memory core chips through a bus and a control signal, and functions as an interface circuit between the plurality of memory core chips and a controller.
In such a semiconductor memory device, in order to check the statuses of the plurality of memory core chips, a status read command is transmitted from the interface chip to the plurality of memory core chips.